The field of the present invention pertains to the field of electronic design automation. More particularly, the present invention pertains to test and floorplanning equivalent processes within the field of electronic design automation of integrated circuit devices.
The rapid growth of the complexity of modern electronic circuits has forced electronic circuit designers to rely upon computer programs to assist and automate most steps of the circuit design process. Typical modem circuits contain hundreds of thousands or millions of individual pieces or xe2x80x9ccells.xe2x80x9d Such a design is much too large for a circuit designer or even an engineering team of designers to manage effectively manually. To automate the circuit design and fabrication of integrated circuit devices, electronic design automation (EDA) systems have been developed.
An EDA system is a computer software system designers use for designing integrated circuit (IC) devices. The EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates this high level design language description into netlists of various levels of abstraction. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives. The generic netlist can be translated by the EDA system into a lower level technology-specific netlist based on a technology-specific library that has gate-specific models for timing and power estimation. A netlist describes the IC design and is composed of nodes (elements) and edges, e.g., connections between nodes, and can be represented using a directed cyclic graph structure having nodes which are connected to each other with signal lines. The netlist is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques. The netlist is then used to generate a physical device layout in mask form which can be used to directly implement structures in silicon to realize the physical IC device.
As ASICs and other complex integrated circuits have become more complex and more dense, they have become progressively harder to test in order to ensure correct and complete functionality. For example, with current technology, as the number of gates and transistors increase, the time which an ASIC spends in testing increases as well. This increase incurs an additional cost on ASIC manufacturing. The testing cost can be very significant for the latest and largest ASIC designs. In addition, as more complex systems-on-a-chip devices proliferate, which, for example, integrate complex logic units (integer units, floating point units, memory, etc.) into a single chip, and as newly-designed processors begin to take advantage of the ability to integrate large quantities of memory on-chip, it has become necessary to increase the comprehensiveness, efficiency, and accuracy of the design checking and testing schemes utilized to ensure proper operation of these devices (e.g., ASICs, complex integrated circuits, field programmable gate arrays, etc.).
Thus, an increasingly important part of the logic synthesis process involves designing for testability. Programs that aid in the testability process of logic synthesis are called. design for test (DFT) processes. One approach to DFT is to take the netlist generated from a compiler and add and/or replace certain memory cells and associated circuitry with special memory cells that are designed to allow the application of test vectors to certain logic portions of the integrated circuit. Test vectors are applied to the design and the special memory cells and associated circuitry are referred to as DFT implementations. The same memory cells can be used to capture the output of the circuitry for observation and compare this output to the expected output in an effort to determine if circuit (e.g., manufacturing) defects are present. Issues concerning controllability deal with facilitating the application of the test vectors to the circuitry to be tested. On the other hand, issues concerning observability deal with facilitating the capturing the output of the circuitry.
The portions of an integrated circuit that are designed to perform its intended or expected operational function are called its xe2x80x9cmission modexe2x80x9d circuitry, while the portions added to the integrated circuit to facilitate testability are called xe2x80x9ctest modexe2x80x9d circuitry or DFT implementations. The resultant circuit, therefore, has two functional modes, mission and test.
An exemplary flow chart diagram of a typical design automation process 100, including a DFT process, is shown in FIG. 1. The process 100 described with respect to this flow chart is implemented within a computer system in a CAD environment. Within the process 100, a circuit designer first generates a high-level description 105 of a circuit in a hardware description language such as VHDL or Verilog. The high-level description 105 is then converted into a netlist 115 by using a computer implemented synthesis process 110 such as the xe2x80x9cDesign Compilerxe2x80x9d available from Synopsys, Inc., of Mountain View, Calif. A netlist 115 is a description of the electronic circuit which specifies what cells compose the circuit and which pins of which cells are to be connected together using interconnects (xe2x80x9cnetsxe2x80x9d). At this point the netlist 115 consists of xe2x80x9cmission modexe2x80x9d circuitry.
At block 120, a constraint-driven scan insertion process is performed to implement testability cells or xe2x80x9ctest modexe2x80x9d cells into the overall integrated circuit design. In this process 120, memory cells of the netlist 115 are replaced with scannable memory cells that are specially designed to apply and observe test vectors or patterns to and from portions of the integrated circuit. In addition, process 120 performs linking groups of scannable memory cells (xe2x80x9cscan cellsxe2x80x9d) into scan chains so that the test vectors can be cycled into and out of the integrated circuit design. The output of the scan insertion process 120 is a scannable netlist 125 that contains both xe2x80x9cmission modexe2x80x9d and xe2x80x9ctest modexe2x80x9d circuitry. Scan insertion process 120 also selects existing functional pins to be used as scan-in and scan-out-ports based on schematic information.
The scannable netlist 125, however, does not contain any information with respect to the physical design of the circuit. For example, the netlist 125 does not specify where the cells are placed on a circuit board or silicon chip, or where the interconnects run. Determining this physical design information is the function of a computer controlled layout process 130.
The layout process 130 first finds a location for each cell on a circuit board or silicon chip. This is called xe2x80x9cplacement.xe2x80x9d The locations are typically selected to optimize certain objectives such as wire length, circuit timing, power consumption, and/or other criteria, and subject to the condition that the cells are spread evenly over the circuit board or silicon chip and that the cells do not overlap with each other. The layout process 130 also generates the wire geometry based on the placement information for connecting the pins of the cells together. The output of the automatic cell layout process 130 includes cell placement data structures and wire geometry data structures 135 that are used to make the final geometric database needed for fabrication of the circuit as shown by process 140.
In some cases, the layout of a typical design is not influenced by the test mode logic. Therefore, the layout process 130 in some cases may break up the scan chains and place the scan cells in such a way that the layout of the mission mode circuitry is not affected. The layout process 130 then reconnects the scan chain based on the placement of the scan cells. This process is also known as placement-based scan chain re-ordering.
One problem associated with process 100 is that the scan-in and scan-out ports used by scan-insertion process 120, which are typically assigned according to schematic information, may not be ideal. For example, the layout process 130 may not be able to optimize certain wire length or circuit timing objectives if inappropriate scan-in and scan-out are used. In addition, poor assignment of the scan-in and scan-out ports may restrict the layout processes from placing scan cells in the best possible positions, and may restrict the placement-based scan chain re-ordering process from determining the best possible ordering of the scan cells.
Accordingly, there exists a need for an IC design automation process that optimizes placement of the scan cells while emphasizing wire routability and circuit timing. What is further needed is an improved process for determining the scan-in and scan-out ports for a scan chain that does not restrict the layout processes and scan-chain re-ordering processes from determining the best placement and best ordering of the scan cells. What is also needed is an improved process for selecting scan-in and scan-out ports for a scan chain such that wire lengths and routing congestion are reduced.
The present invention provides an improved IC design automation process that optimizes placement of the scan cells while emphasizing wire routability and circuit timing. The present invention also provides a method of selecting scan-in and scan-out ports that allows the scan cells to be placed in the best possible position and allows scan-chain re-ordering processes to determine the best possible ordering for the scan chain. In addition, the present invention provides a method of selecting scan-in and scan-out ports for a scan chain such that wire lengths and routing congestion are reduced. These and others advantages of the present invention not specifically mentioned above will become clear within discussions presented herein.
According to one embodiment of the present invention, scan cells are inserted into a netlist description of an integrated circuit design and are coupled serially together to form a scan chain. The resulting netlist is then passed to layout processes where the cells of the integrated circuit design are automatically placed and routed. Significantly, the layout processes are performed without regard to any constraints that designate particular functional pins as scan-in and scan-out. In accordance with the present invention, scan-in and scan-out ports are then selected based on the placement of the scan cells such that routing wire lengths and routing congestion are minimized. Thus, by avoiding predefined scan-in and scan-out processes, the present invention improves cell placement and wire routability and allows a better integrated circuit to be designed and fabricated.
In another embodiment of the present invention, scan cells of a scan chain are re-ordered based on placement information during the layout processes. Importantly, the layout processes (including placement processes and scan chain re-ordering processes) are performed without regard to any constraint or definition that designates particular functional pins as scan-in and scan-out ports. Scan-in and scan-out ports of the re-ordered scan chain are subsequently selected based on the final placement of the scan cells such that routing wire lengths and routing congestion are minimized. In particular, the port selected as the scan-in port is the port closest to the final position of the leading scan cell of the scan chain. The port selected as the scan-out port is the port closest to the final position of the last scan cell of the scan chain. In this manner, an even more effective cell placement can be achieved.
In yet another embodiment of the present invention, place-and-route processes, scan-chain re-ordering processes and ports selection process are performed without regard to any constraints designating any functional pin as scan-in and scan-out. Rather, these processes use the wirelengths from the functional pins to the scan cells as constraints when placing and re-ordering the scan cells, and when selecting scan-in and scan-out ports for the scan chain. The best placement, scan-chain order and scan-in and scan-out ports can then be determined heuristically.
In yet another embodiment, the scan cells of the scan chain are partitioned into sets of re-orderable scan cells. Data representative of the resulting sets is then provided to layout processes and therein the scan cells of the scan chain are re-ordered based on the sets. Further, the layout processes are performed without regard to any constraints that designate particular functional pins as scan-in and scan-out. After the scan cells are placed, functional pins are selected and used as scan-in and scan-out ports of the re-ordered scan chain such that routing wire length and routing congestion are reduced. In this manner, the efficiency and effectiveness of the layout processes is improved.
Embodiments of the present invention include the above and further include an improved computer-aided design (CAD) system that inserts a scan chain within an integrated design, and places and routes the integrated circuit design to determine its layout without regard to any predetermined constraint designating a functional pin as a scan-in port or a scan-out port for the scan chain. Rather, the CAD system selects the scan-in and scan-out ports based on placement. The CAD system then modifies the netlist description of the integrated circuit design to add scan-in functionality and scan-out functionality to the selected functional pins, thereby improving cell placement and wire routability, and allowing a better designed integrated circuit to be designed and fabricated.